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january 2012 doc id 18134 rev 2 1/32 32 L6738A single-phase pwm controller with light-load efficiency optimization features flexible power supply from 5 v to 12 v bus power conversion input as low as 1.5 v light-load efficiency optimization embedded bootstrap diode vin detector 0.8 v internal reference 0.5% output voltage accuracy remote gnd recovery high-current integrated drivers sensorless and programmable precise-oc sense across inductor dcr ov protection programmable oscillator up to 600 khz ls-less to manage pre-bias startup adjustable output voltage disable function internal soft-start vfqfpn 16 3x3 mm package applications memory and termination supply subsystem power supply (mch, ioch, pci) cpu and dsp power supply distributed power supply general dc-dc converter description the L6738A is a single-phase step-down controller with integrated high-current drivers that provides complete control logic and protection to realize a dc-dc converter. the device flexibility allows to manage conversions with power input v in as low as 1.5v and the device supply voltage ranging from 5 v to 12 v bus. the L6738A features a proprietary algorithm that allows light-load efficiency optimization, boosting efficiency without compromising the output voltage ripple. the integrated 0.8 v reference allows generation of output voltages with 0.5% accuracy over line and temperature variations. the oscillator is programmable up to 600 khz. the L6738A provides a programmable overcurrent protection and overvoltage protection. the current information is monitored across the inductor dcr. the L6738A is available in a vfqfpn 16 3x3 mm package. table 1. device summary order code package packing L6738A vfqfpn16 tube L6738A tr vfqfpn16 tape and reel vfqfpn16 www.st.com
contents L6738A 2/32 doc id 18134 rev 2 contents 1 typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 5 1.1 application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 pin description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 device description and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 ls-less startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 output voltage setting and protections . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1 overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 overcurrent threshold setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8 high current embedded drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.1 boot capacitor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.2 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9 application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.1 compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.2 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 10 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10.1 inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10.2 output capacitor(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
L6738A contents doc id 18134 rev 2 3/32 10.3 input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 11 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
list of tables L6738A 4/32 doc id 18134 rev 2 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 5. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 6. L6738A protection at a glance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 7. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
L6738A list of figures doc id 18134 rev 2 5/32 list of figures figure 1. typical application circuit (fast protections) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5. ls-less startup (left) vs. non-ls-less startup (right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 6. current reading network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 7. rosc vs. switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 8. bootstrap capacitor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 9. pwm control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 10. example of type iii compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 11. power connections (heavy lines) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 12. drivers turn-on and turn-off paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 13. inductor current ripple vs. output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 14. vfqfpn16 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
typical application circuit and block diagram L6738A 6/32 doc id 18134 rev 2 1 typical application circuit and block diagram 1.1 application circuit figure 1. typical application circuit (fast protections) boot ugate pha s e lgate h s l s v in = 1.5v to 19v l c out vo u t load c hf c bulk c dec fb r fb comp r f c f c p vcc v cc = 5v to 12v l67 38 a reference s chem a tic l67 38 a r o s r c gnd fbg c s p c s n v s en r i c i en pgood pgood en vccdr o s c c dec r o s c
L6738A typical application circuit and block diagram doc id 18134 rev 2 7/32 figure 2. typical application circuit boot ugate pha s e lgate h s l s v in = 1.5v to 19v l c out vo u t load c hf c bulk c dec fb r fb comp r f c f c p vcc v cc = 5v to 12v l67 38 a reference s chem a tic l67 38 a r o s r c gnd r fb r o s fbg c s p c s n v s en r i c i en pgood pgood en vccdr o s c c dec r o s c
typical application circuit and block diagram L6738A 8/32 doc id 18134 rev 2 1.2 block diagram figure 3. block diagram vcc boot lgate fb ugate comp gnd adaptive anti cross conduction hs ls error amplifier + - 0. 8 0v programmable oscillator pwm phase control logic, monitor, protections & efficiency optimization l67 38 a clock over current csp csn 2.2 vccdr en o s c v s en +25 % -25 % ovp uvp ovp uvp pgood ocp fbg 10k 10k
L6738A pin description and connection diagrams doc id 18134 rev 2 9/32 2 pin description and connection diagrams figure 4. pin connection (top view) 2.1 pin descriptions 1 2 3 v s en fbg vccdr 12 6 10 11 l67 38 a lgate pha s e c s n 7 5 16 15 14 gnd vcc o s c ugate pgood en boot 4 comp 8 fb 9 1 3 c s p table 2. pin description pin# name function 1 vccdr low side driver section power supply. operative voltage is 5 v to 12 v bus. filter with 1 f mlcc to gnd. 2lgate low-side driver output. connect directly to the low-side mosfet gate. a small series resistor can be useful to reduce dissipated power especially in high frequency applications. 3 phase high-side driver return path. connect to the high-side mosfet source. this pin is also monitored for the adaptive dead-time management. 4boot high-side driver supply. this pin supplies the high-side floating driver. connect through the c boot capacitor to the phase pin. the pin is internally connected through a boot diode to the vccdr pin. a 2.2ohm series resistor is also provided. see section 8 for guidance in designing the capacitor value. 5ugate high-side driver output. connect to high-side mosfet gate. a small series resistor may help in reducing the phase pin negative spike as well as cooling the device. 6 pgood power good. it is an open-drain output set free after ss (with 3x clock cycle delay) as long as the out- put voltage monitored through vsen is within specifications. pull-up to 3.3 v (typ) or lower, if not used it can be left floating. 7en enable pin. pull-high to <5 v to enable conversion, 10 a pull-down provided.
pin description and connection diagrams L6738A 10/32 doc id 18134 rev 2 2.2 thermal data 8comp error amplifier output. connect with an r f - c f to fb. the device cannot be disabled by grounding this pin. 9fb error amplifier inverting input. connect with a resistor r fb to vsen and with an r f - c f to comp. 10 vsen output voltage monitor. it manages ovp and uvp protections and pgood. connect to the positive side of the load for remote sensing. see section 6 for details. 11 fbg remote ground sense. connect to the negative side of the load for remote sensing. 12 csn current sense negative input. connect to the output-side of the main inductor. filter with 100 nf (typ.) to gnd. 13 csp current sense positive input. connect through an r-c filter to the phase-side of the main inductor. 14 osc osc: internally set to 1.24 v, it allows programming the switching frequency f sw of the device. switching frequency can be increased according to the resistor r osc connected to sgnd with a gain of 10 khz/a (see section 7 for details). if floating, the switching fre- quency is 200 khz. 15 vcc device power supply. the embedded bootstrap diode is internally connected to this pin. operative voltage is 5 v to 12 v bus. filter with 1 f mlcc to gnd. for proper operations, vcc needs to be >1.5 v higher than the programmed v out . 16 gnd all internal references, logic and driver return path are referenced to this pin. connect to the pcb gnd ground plane and filter to vcc and vccdr. thermal pa d the thermal pad connects the silicon substrate and makes good thermal contact with the pcb. use vias to connect to the pgnd plane. table 2. pin description (continued) pin# name function table 3. thermal data symbol parameter value unit r thja thermal resistance junction to ambient (device soldered on 2s2p pc board) 45 c/w r thjc thermal resistance junction to case 1 c/w t max maximum junction temperature 150 c t stg storage temperature range -40 to 150 c t j junction temperature range -40 to 125 c
L6738A electrical specifications doc id 18134 rev 2 11/32 3 electrical specifications 3.1 absolute maximum ratings 3.2 electrical characteristics (v cc = 5 v to 12 v; t j = 0 to 70 c unless otherwise specified). table 4. absolute maximum ratings symbol parameter value unit v cc, v ccdr to gnd -0.3 to 15 v v boot , v ugate to gnd to phase to gnd, vccdr = 12 v, t < 200 nsec. -0.3 to 41 15 45 v v phase to gnd to gnd, vccdr = 12 v, t < 200 nsec. -5 to 26 -8 to 30 v v lgate to gnd -0.3 to vccdr + 0.3 v en to gnd, vcc < 7 v to gnd, vcc > 7 v -0.3 to vcc + 0.3 -0.3 to 7 v csp, csn to gnd (1) 1. current sense network needs to be properly bias and loop closed. -0.3 to vcc - 1.5 v all other pins to gnd -0.3 to 3.6 v table 5. electrical characteristics symbol parameter test conditions min. typ. max. unit supply current and power-on i cc vcc supply current en = high 9 ma en = gnd 8 ma i ccdr vccdr supply current ugate and lgate = open 2.6 ma en = gnd ugate and lgate = open 0.3 ma uvlo vcc, uvlo vccdr turn-on threshold vcc, vccdr rising 4.1 v hysteresis 0.2 v oscillator enable and soft-start f sw main oscillator accuracy osc = open 180 200 220 khz k osc oscillator gain current sink/source from osc 10 khz/ a tss soft-start time osc = open 4.5 5.12 5.7 msec tssdelay ss delay osc = open, before ss 4.5 5.12 5.7 msec
electrical specifications L6738A 12/32 doc id 18134 rev 2 ? v osc pwm ramp amplitude 2 v d duty cycle 0 100 % en input logic high en rising 0.9 v input logic low en falling 0.5 v reference and error amplifier output voltage accuracy vout to fbg -0.5 - 0.5 % a 0 dc gain (1) 120 db gbwp gain-bandwidth product (1) 15 mhz sr slew-rate (1) 8v/ s gate driver i ugate hs source current (1) boot - phase = 12 v; c ugate to phase = 3.3 nf 2a r ugate hs sink resistance boot - phase = 12 v; 100 ma 2 2.5 ? i lgate ls source current (1) c lgate to gnd = 5.6 nf 3 a r lgate ls sink resistance 100 ma 1 1.5 ? current sense amplifier v octh oc current threshold csp - csn; 7x masking 17 20 23 mv pgood and protection pgood ovp threshold vsen rising 0.870 0.900 0.930 v un-latch, vsen falling 0.350 0.400 0.450 v uvp threshold vsen falling 0.570 0.600 0.630 v 1. guaranteed by design, not subject to test. table 5. electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit
L6738A device description and operation doc id 18134 rev 2 13/32 4 device description and operation the L6738A is a single-phase pwm controller with embedded high-current drivers that provides complete control logic and protections to realize a general dc-dc step-down converter. designed to drive n-channel mosfets in a synchronous buck topology, with its high level of integration, this 16-pin device allows a reduction of cost and size of the power supply solution and also provides real-time pgood in a compact vfqfpn16 3x3 mm. the L6738A is designed to operate from a 5 v or 12 v supply. the output voltage can be precisely regulated to as low as 0.8 v with 0.5% accuracy over line and temperature variations. the controller performs remote gnd recovery to prevent losses and gnd drops to affect the regulation. the switching frequency is internally set to 200 khz and adjustable through the osc pin. the ic can be disabled by pulling the osc pin low. the L6738A provides a simple control loop with a voltage-mode error-amplifier. the error- amplifier features a 15 mhz gain-bandwidth product and 8 v/s slew rate, allowing high regulator bandwidth for fast transient response. to avoid load damages, the L6738A provides overcurrent protection, and overvoltage and undervoltage protection. the overcurrent trip threshold is monitored through the inductor dcr, assuring optimum precision, saving the use of an expensive and space-consuming sense resistor. the output voltage is monitored through the dedicated vsen pin. the L6738A implements soft-start by increasing the internal reference in closed loop regulation. the low-side-less feature allows the device to perform the soft-start over pre- biased output avoiding high current return through the output inductor and dangerous negative spikes at the load side. the L6738A is available in a compact vfqfn16 3x3 mm package with exposed pad.
soft-start L6738A 14/32 doc id 18134 rev 2 5 soft-start the L6738A implements a soft-start to smoothly charge the output filter avoiding high in- rush currents to be required to the input power supply. during this phase, the device increases the internal reference from zero up to 0.8 v in closed loop regulation. the soft- start is implemented only when vcc and vccdr are above their own uvlo threshold and the en pin is set free. when ss takes place, the ic initially waits for 1024 clock cycles and then starts ramping-up the reference in 1024 clock cycles in closed-loop regulation. at the end of the digital soft- start, the pwrgood signal is set free with 3x clock cycles delay. protections are active during this phase as follows: undervoltage is enabled when the reference voltage reaches 80% of the final value overvoltage is always enabled fb disconnection is enabled soft-start time depends on the programmed frequency, initial delay and reference ramp-up lasts for 1024 clock cycles. ss time and initial delay can be determined as follows: 5.1 ls-less startup in order to avoid any kind of negative undershoot on the load side during startup, the L6738A performs a special sequence in enabling the drivers for both sections: during the soft-start phase, the ls mosfet is kept off until the first pwm pulse. this particular sequence avoids the dangerous negative spike on the output voltage that can happen if starting over a pre-biased output. low-side mosfet turn-on is masked only from the control loop point of view: protections are still allowed to turn on the low-side mosfet in the case of overvoltage, if needed. t ss ms [] 1024 fsw khz ] [] ------------------------------ =
L6738A soft-start doc id 18134 rev 2 15/32 figure 5. ls-less startup (left) vs. non-ls-less startup (right)
output voltage setting and protections L6738A 16/32 doc id 18134 rev 2 6 output voltage setting and protections the L6738A is capable of precisely regulating an output voltage as low as 0.8 v. in fact, the device comes with a fixed 0.8 v internal reference that guarantees the output regulated voltage to be within 0.5% tolerance over line and temperature variations (excluding output resistor divider tolerance, when present). output voltage higher than 0.8 v can be easily achieved by adding a resistor r os between the fb pin and ground. referring to figure 1 , the steady-state dc output voltage is: where v ref is 0.8 v. the L6738A monitors the voltage at the vsen pin and compares it to the internal reference voltage in order to provide undervoltage and overvoltage protections, as well as pgood signal. according to the level of vsen, different actions are performed from the controller: pgood if the voltage monitored through vsen exits from the pgood window limits, the device de-asserts the pgood signal. pgood is asserted at the end of the soft-start phase with 3x clock cycles delay. undervoltage protection (uv) if the voltage at the vsen pin drops below the uv threshold, the device turns off both hs and ls mosfets, latching the condition. cycle vcc or en to recover. uv is also active during ss acting as vin detection protection. see description below. overvoltage protection (ov) if the voltage at the vsen pin rises over the ov threshold, overvoltage protection turns off the hs mosfet and turns on the ls mosfet. the ls mosfet is turned off as soon as vsen goes below vref/2. the condition is latched, cycle vcc/en to recover. note that, even if the device is latched, the device still controls the ls mosfet and can switch it on whenever vsen rises above the ov threshold. preovp protection monitors vsen when ic is disabled. if vsen surpasses the ov threshold, ic turns on the low-side mosfet to protect the load. on the en rising edge, the protection is disabled and the ic implements the ss procedure. preovp is disabled when en is high but the ov protection becomes operative. vin detection uv protection active during ss allows the ic to detect whether input voltage vin is present. if uv is triggered during the soft-start, it resets the ss procedure: the controller re-implements the initial delay and re-ramps-up the reference with the same ss timings described in section 5 . the uv protection is then avoiding that ic starts-up if vin is not present. protections are active also during soft-start (see section 5 ). v out v ref 1 r fb r os ----------- + ?? ?? ? =
L6738A output voltage setting and protections doc id 18134 rev 2 17/32 for proper operations, vcc needs to be at least 1.5 v higher than the programmed output voltage. table 6. L6738A protection at a glance. 6.1 overcurrent the overcurrent function protects the converter from a shorted output or overload, by sensing the output current information across the inductor dcr. this method reduces cost and enhances converter efficiency by avoiding the use of expensive and space-consuming sense resistors. the inductor dcr current sense is implemented by comparing and monitoring the difference between the csp and csn pins. if the monitored voltage is bigger than the internal thresholds, an overcurrent event is detected. dcr current sensing requires time constant matching between the inductor and the reading network: the L6738A monitors the voltage between csp and csn, when this voltage exceeds the oc threshold, an overcurrent is detected. the ic works in constant current mode, turning on the low-side mosfet immediately while the oc persists and, in any case, until the next clock cycle. after seven consecutive oc events, overcurrent protection is triggered and the ic latches. when overcurrent protection is triggered, the device turns off both ls and hs mosfets in a latched condition. to recover from an overcurrent protection triggered condition, vcc power supply or en must be cycled. for proper current reading, the csn pin must be filtered by 100 nf (typ.) mlcc to gnd. L6738A comments overvoltage (ov) vsen = +12.5% above reference. action: ic latch; ls=on until vsen = 50% of vref; pgood = gnd. action (en=0): ic latch; ls=on; reset by en rising edge (preovp). undervoltage (uv) vsen = -25% below reference. action: ic latch; hiz; pgood = gnd. action (ss): ss reset (vin detection). pgood pgood is set to zero whenever vsen falls outside the +12.5% / -25% of vref. action: pgood transition coincides with ov/uv protection set. overcurrent (oc) current monitor across inductor dcr. action: 1st threshold (20 mv): ic latch after 7 consecutive constant current events. l dcr ------------- rc v csp-csn dcr i out ? = ? ? =
output voltage setting and protections L6738A 18/32 doc id 18134 rev 2 6.2 overcurrent threshold setting the L6738A detects oc when the difference between csp and csn is equal to 20 mv (typ). by properly designing the current reading network, it is possible to program the oc threshold as desired (see figure 6 ). time constant matching is, in this case, designed considering: this means that once inductor has been chosen, the two conditions above define the proper values for r1 and r2. figure 6. current reading network i ocp 20mv dcr --------------- - r1 r2 + r2 --------------------- - ? = l dcr ------------- r1//r2 () c ? = l c r1 c s p c s n r2 (opt) dcr
L6738A main oscillator doc id 18134 rev 2 19/32 7 main oscillator the controller embeds a programmable oscillator. the internal oscillator generates the sawtooth waveform for the pwm charging with a constant current and resetting an internal capacitor. the switching frequency, f sw , is internally fixed at 200 khz. the current delivered to the oscillator is typically 20 a (corresponding to the free running frequency f sw =200 khz) and it may be varied using an external resistor (r osc ) typically connected between the osc pin and gnd. as the osc pin is fixed at 1.240 v, the frequency is varied proportionally to the current sunk from the pin considering the internal gain of 10 khz/ a (see figure 7 ). connecting r osc to gnd, the frequency is increased (current is sunk from the pin), according to the following relationships: connecting r osc to a positive voltage, the frequency is reduced (current is forced into the pin), according to the following relationships: where +v is the positive voltage to which the r osc resistor is connected. figure 7. r osc vs. switching frequency f sw 200khz 1.240v r osc ------------------ - 10 khz a ---------- - ? + = f sw 200khz +v 1.240 ? r osc ---------------------------- 10 khz a ---------- - ? ? =
high current embedded drivers L6738A 20/32 doc id 18134 rev 2 8 high current embedded drivers the L6738A provides high-current driving control. the driver for the high-side mosfet uses the boot pin for supply and the phase pin for return. the driver for the low-side mosfet uses the vccdr pin for supply and the gnd pin for return. the embedded driver embodies an anti-shoot-through and adaptive dead-time control to minimize the low-side body diode conduction time maintaining good efficiency and saving the use of schottky diodes: when the high-side mosfet turns off, the voltage on its source begins to fall; when the voltage reaches about 2 v, the low-side mosfet gate drive voltage is suddenly applied. when the low-side mosfet turns off, the voltage at the lgate pin is sensed. when it drops below about 1 v, the high-side mosfet gate drive voltage is suddenly applied. if the current flowing in the inductor is negative, the source of the high- side mosfet never drops. to allow the low-side mosfet to turn on even in this case, a watchdog controller is enabled: if the source of the high-side mosfet doesn't drop, the low- side mosfet is switched on, so allowing the negative current of the inductor to recirculate. this mechanism allows the system to regulate even if the current is negative. 8.1 boot capacitor design the bootstrap capacitor needs to be designed in order to show a negligible discharge due to the high-side mosfet turn on. in fact, it must give a stable voltage supply to the high-side driver during the mosfet turn on, also minimizing the power dissipated by the embedded boot diode. figure 8 gives some guidelines on how to select the capacitance value for the bootstrap according to the desired discharge and depending on the selected mosfet. to prevent the bootstrap capacitor to extra-charge as a consequence of large negative spikes, an internal 2.2 ohms series resistance r boot is provided in series to the boot diode pin. figure 8. bootstrap capacitor design 8.2 power dissipation it is important to consider the power that the device is going to dissipate in driving the exter- nal mosfets in order to avoid surpassing the maximum junction operative temperature. 0.0 0.5 1.0 1.5 2.0 2.5 01020 3 040506070 8 090100 boot c a p di s ch a rge [v] high - s ide mo s fet g a te ch a rge [nc] c b oot = 47nf c b oot = 100nf c b oot = 220nf c b oot = 33 0nf c b oot = 470nf 0 500 1000 1500 2000 2500 0.0 0.2 0.4 0.6 0. 8 1.0 boot s tr a p c a p [ u f] boot c a p delt a volt a ge [v] qg = 10nc qg = 25nc qg = 50nc qg = 100nc
L6738A high current embedded drivers doc id 18134 rev 2 21/32 two main terms contribute in the device power dissipation: bias power and drivers' power. device power (p dc ) depends on the static consumption of the device through the supply pins and it is simply quantifiable as follows: drivers' power is the power needed by the driver to continuously switch on and off the external mosfets; it is a function of the switching frequency and total gate charge of the selected mosfets. it can be quantified considering that the total power p sw , dissipated to switch the mosfets, is dissipated by three main factors: external gate resistance (when present), intrinsic mosfet resistance and intrinsic driver resistance. this last term is the important one to be determined to calculate the device power dissipation. the total power dissipated to switch the mosfets for each phase featuring embedded driver results: where q ghs is the total gate charge of the hs mosfets and q gls is the total gate charge of the ls mosfets. p dc v cc i cc v vccdr i vccdr ? + ? = p sw f sw q ghs vccdr ? q gls vccdr ? + () ? =
application details L6738A 22/32 doc id 18134 rev 2 9 application details 9.1 compensation network the control loop shown in figure 9 is a voltage mode control loop. the output voltage is regulated to the internal reference (when present, an offset resistor between fb node and gnd can be neglected in control loop calculation). error amplifier output is compared to the oscillator sawtooth waveform to provide a pwm signal to the driver section. the pwm signal is then transferred to the switching node with v in amplitude. this waveform is filtered by the output filter. the converter transfer function is the small signal transfer function between the output of the ea and v out . this function has a double pole at frequency f lc depending on the l-c out resonance and a zero at f esr depending on the output capacitor esr. the dc gain of the modulator is simply the input voltage v in divided by the peak-to-peak oscillator voltage ? v osc . figure 9. pwm control loop the compensation network closes the loop joining v out and ea output with transfer function ideally equal to -z f / z fb . compensation goal is to close to the control loop assuring high dc regulation accuracy, good dynamic performance and stability. to achieve this, the overall loop needs high dc gain, high bandwidth and good phase margin. high dc gain is achieved giving an integrator shape to compensation network transfer function. loop bandwidth (f 0db ) can be fixed choosing the right r f /r fb ratio, however, for stability, it should not exceed f sw /2 . to achieve a good phase margin, the control loop gain has to cross the 0db axis with -20db/decade slope. for example, figure 10 shows an asymptotic bode plot of a type iii compensation. l r c out esr r f c f c p r fb c s osc v in ? v osc + + _ _ v out v ref z f z fb pwm comparator error amplifier r s
L6738A application details doc id 18134 rev 2 23/32 figure 10. example of type iii compensation. open loop converter singularities: a) b) compensation network singularities frequencies: a) b) c) d) to place the poles and zeros of the compensation network, the following suggestions may be followed: gain [db] log (freq) 0db open loop ea gain closed loop gain compensation gain open loop converter gain f lc f esr f z1 f z2 f p1 f p2 20log (r f /r fb ) 20log (v in / ? v osc ) f 0db f lc 1 2 lc out ? ------------------------------------ - = f esr 1 2 c out esr ?? ------------------------------------------------- = f z1 1 2 r f c f ?? ----------------------------------- - = f z2 1 2 r fb r s + () c s ?? ---------------------------------------------------------- = f p1 1 2 r f c f c p ? c f c p + --------------------- - ?? ?? ?? -------------------------------------------------------- = f p2 1 2 r s c s ?? ------------------------------------ =
application details L6738A 24/32 doc id 18134 rev 2 a) set the gain r f /r fb in order to obtain the desired closed loop regulator bandwidth according to the approximated formula (suggested values for r fb are in the range of some k ? ): b) place f z1 below f lc (typically 0.5*f lc ): c) place f p1 at f esr : d) place f z2 at f lc and f p2 at half of the switching frequency: e) check that compensation network gain is lower than open loop ea gain before f 0db ; f) check phase margin obtained (it should be greater than 45) and repeat if necessary. 9.2 layout guidelines the L6738A provides control functions and high current integrated drivers to implement high-current step-down dc-dc converters. in this kind of application, a good layout is very important. the first priority when placing components for these applications has to be reserved to the power section, minimizing the length of each connection and loop as much as possible. to minimize noise and voltage spikes (emi and losses) power connections (highlighted in figure 11 ) must be a part of a power plane and realized by wide and thick copper traces: loop must be minimized. the critical components, i.e. the power mosfets, must be close to one another. the use of a multi-layer printed circuit board is recommended. the input capacitance (c in ), or at least a portion of the total capacitance needed, has to be placed close to the power section in order to eliminate the stray inductance generated by the copper traces. low esr and esl capacitors are preferred, mlccs are recommended to be connected near the hs drain. use a proper number of vias when power traces have to move between different planes on the pcb in order to reduce both parasitic resistance and inductance. moreover, reproducing the same high-current trace on more than one pcb layer reduces the parasitic resistance associated to that connection. r f r fb ---------- f 0db f lc ------------ ? v osc v in ------------------ - ? = c f 1 r f f lc ?? ---------------------------------- - = c p c f 2 r f c f f esr 1 ? ??? ------------------------------------------------------------------ - = r s r fb f sw 2f ? lc -------------------- 1 ? ----------------------------- - = c s 1 r s f sw ?? ------------------------------------ - =
L6738A application details doc id 18134 rev 2 25/32 connect output bulk capacitors (c out ) as near as possible to the load, minimizing parasitic inductance and resistance associated to the copper trace, also adding extra decoupling capacitors along the way to the load when this results in being far from the bulk capacitors bank. remote sense connection must be routed as parallel nets from the fbg/vsen pins to the load in order to avoid the pick-up of any common mode noise. connecting these pins in points far from the load causes a non-optimum load regulation, increasing output tolerance. locate current reading components close to the device. the pcb traces connecting the reading point must use dedicated nets, routed as parallel traces in order to avoid the pick-up of any common mode noise. it's also important, to avoid any offset in the measurement and, to get a better precision, to connect the traces as close as possible to the sensing elements. a small filtering capacitor can be added, near the controller, between vout and gnd, on the csn line to allow higher layout flexibility. figure 11. power connections (heavy lines) gate traces and phase trace must be sized according to the driver rms current delivered to the power mosfet. the device robustness allows the managing of applications with the power section far from the controller without losing performance. however, when possible, it is recommended to minimize the distance between the controller and power section. small signal components and connections to critical nodes of the application, as well as bypass capacitors for the device supply, are also important. locate the bypass capacitor (vcc and bootstrap capacitor) and feedback compensation components as close to the device as practical. figure 12. drivers turn-on and turn-off paths l c in v in ugate phase lgate gnd load l6738 c out r gate r int c gd c g s c d s vccdr l s driver l s mo s fet gnd lgate r gate r int c gd c g s c d s boot h s driver h s mo s fet pha s e ugate
application information L6738A 26/32 doc id 18134 rev 2 10 application information 10.1 inductor design the inductance value is defined by a compromise between the dynamic response time, the efficiency, the cost, and the size. the inductor must be calculated to maintain the ripple current ( ? i l ) between 20% and 30% of the maximum output current (typ). the inductance value can be calculated with the following relationship: where f sw is the switching frequency, v in is the input voltage and v out is the output voltage. figure 13 shows the ripple current vs. the output voltage for different values of the inductor, with v in = 5 v and v in = 12 v. increasing the value of the inductance reduces the current ripple but, at the same time, increases the converter response time to a dynamic load change. the response time is the time required by the inductor to change its current from initial to final value. until the inductor has finished its charging time, the output current is supplied by the output capacitors. minimizing the response time can minimize the output capacitance required. if the compensation network is well designed, during a load variation the device is able to set a duty cycle value very different (0% or 80%) from the steady-state one. when this condition is reached, the response time is limited by the time required to change the inductor current. figure 13. inductor current ripple vs. output voltage l v in v out ? f sw ? i l ? ----------------------------- - v out v in -------------- ? =
L6738A application information doc id 18134 rev 2 27/32 10.2 output capacitor(s) the output capacitors are basic components to define the ripple voltage across the output and for the fast transient response of the power supply. they depend on the output voltage ripple requirements, as well as any output voltage deviation requirement during a load transient. during steady-state conditions, the output voltage ripple is influenced by both the esr and capacitive value of the output capacitors as follows: where ? i l is the inductor current ripple. in particular, the expression that defines ? v out_c takes into consideration the output capacitor charge and discharge as a consequence of the inductor current ripple. during a load variation, the output capacitors supply the current to the load or absorb the current stored in the inductor until the converter reacts. in fact, even if the controller immediately recognizes the load transient and sets the duty cycle at 80% or 0%, the current slope is limited by the inductor value. the output voltage has a drop that, also in this case, depends on the esr and capacitive charge/discharge as follows: where ? v l is the voltage applied to the inductor during the transient response ( for the load appliance or v out for the load removal). mlcc capacitors have typically low esr to minimize the ripple but also have low capacitance which does not minimize the voltage deviation during dynamic load variations. on the contrary, electrolytic capacitors have large capacitance to minimize voltage deviation during load transients while they do not show the same esr values as the mlcc resulting ? v out_esr ? i l esr ? = ? v out_c ? i l 1 8c out f sw ?? -------------------------------------------- ? = ? v out_esr ? i out esr ? = ? v out_c ? i out l ? i out ? 2c out ? v l ?? ------------------------------------------- ? = d max v in v out ? ?
application information L6738A 28/32 doc id 18134 rev 2 therefore in higher ripple voltages. for these reasons, a mix between electrolytic and mlcc capacitors is suggested to minimize ripple as well as reduce voltage deviation in dynamic mode. 10.3 input capacitors the input capacitor bank is designed considering mainly the input rms current that depends on the output deliverable current (i out ) and the duty-cycle (d) for the regulation as follows: the equation reaches its maximum value, i out /2, with d = 0.5. the losses depend on the input capacitor esr and, in the worst case, are: i rms i out d1d ? () ? ? = p esr i out 2 ? () 2 ? =
L6738A package mechanical data doc id 18134 rev 2 29/32 11 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions, and product status are available at www.st.com . ecopack is an st registered trademark.
package mechanical data L6738A 30/32 doc id 18134 rev 2 figure 14. vfqfpn16 mechanical data and package dimensions outline and mechanical data dim. mm mils min. typ. max. min. typ. max. a vfqfpn-16 (3x3x1.0mm) v ery f ine q uad f lat p ackage n o lead 0.80 0.90 1.00 31.49 35.43 39.37 a1 0.02 0.05 0.78 1.96 a2 0.65 1.00 25.59 39.37 a3 0.20 7.87 b 0.18 0.25 0.30 7.08 9.84 11.81 d 2.85 3.00 3.15 112.2 118.1 124.0 d1 1.50 59.05 d2 1.60 62.99 e 2.85 3.00 3.15 112.2 118.1 124.0 e1 1.50 59.05 e2 1.60 62.99 e 0.45 0.50 0.55 17.71 19.68 21.65 l 0.30 0.40 0.50 11.81 15.74 19.68 ddd 0.08 3.15
L6738A revision history doc id 18134 rev 2 31/32 12 revision history table 7. document revision history date revision changes 03-nov-2010 1 initial release. 23-jan-2012 2 updated pgood limits in ta bl e 5
L6738A 32/32 doc id 18134 rev 2 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in military, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2012 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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